Why do we need to protect vias? Here to answer is Gerry Partida, Director of Engineering at Summit Interconnect Technologies. Summit is an advanced technology manufacturer creating custom printed circuit boards. Summit focuses on complex rigid and rigid-flex products and offers extensive expertise in RF/Microwave applications. In today’s episode, Gerry will help us untangle IPC 4761 and get actionable info that you can apply to your designs.

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Show Highlights:

  • IPC 4761 comprises design guidelines on seven existing methods of via protection
  • Combinations: Capping one side vs the other side, dry film soldermask with soldermask over, or via plugged with solder mask capped over with soldermask or not, plated shut via epoxy filled and plated over, or via and pad also known as Type 7 which is popular for HDI (High Density Interconnect)
  • Why protect Vias? To prevent solder paste from running down an open via to the other side of the board, preventing solder balls on the secondary side, moisture protection, sealing to prevent chemistry entering and becoming trapped, to ease the subsequent processes, and finally assembly
  • For via protection with a surface finish like ENIG or ENEPIG, both sides of the via need to be open during the ENIG or ENEPIG process.
  • IPC 6012 Class 3 now prescribes the same thickness for copper wrap plating
  • Why do people fill? Primary reason is to get the via at the pad connection in the component
  • When you’re talking about High Speed Digital, you don’t want to go from trace to via
  • Place via in land to avoid delay and reduced real estate for routing
  • Slight reduction in reliability when via is plated, epoxy-filled and plated over versus a via only plated in the final
  • Peel strength is much lower when you epoxy-fill is in the center and plated over
  • You have to buy IPC standards
  • Encroach soldermask clearances - encroaching soldermask on top of the LAN but not in the hole is an excellent solution.


Links and Resources:

Summit Interconnect

IPC standards


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